Resonant Clock Generation

Proliferations of portable devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital system and is known to consume large amount the power budget of the current processor. This paper describes the importance of the sinusoidal clock in low power clock circuits and synchronous resonance clock generator for clock generation. The frequency range is 830MHz. In this paper we are going to analyze the synchronous PCG (power clock generator). Experimental results show that the 2N synchronous clock generator is less sensitive to capacitance imbalance than the 2N2P clock generator. The circuit performance is evaluated by changing the capacitance values and simulated in Tanner EDA tool.